EDN

Efficient checks for cache-coherency verification in complex SoCs

Cache, in its crude definition, is a faster memory which stores copies of data from frequently used main memory locations. Nowadays, multiprocessor systems are supporting shared memories in hardware, ...
Yahoo Finance

Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies

SAN JOSE, Calif., June 30, 2022 (GLOBE NEWSWIRE) -- Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC ...
Design-Reuse

Building Your UVM Verification Environment for Cache Coherent Interconnects

The ARM® AMBA® 4 Coherency Extension (ACE™) specification was officially published more than a year ago. The main driver for the ACE spec is the need to support hardware-managed cache coherency, ...
AOL

Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Perfor

Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs "Many teams in multi-core SoC design are moving to ...
Design-Reuse

Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs

WILSONVILLE, Ore., June 3, 2013 —Mentor Graphics Corp. (NASDAQ: MENT) today announced that cache coherent interconnect subsystem verification has been added to the Questa® and Veloce® platforms.
EDN

Synopsys Delivers Industry’s First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect

The Synopsys cache coherent NoC subsystem verification solution generates UVM testbench logic that integrates with Arteris Ncore interconnect testbenches, enabling connectivity of new subsystem level ...