Design-Reuse

VLSI Plus offers Multiple Pixel per Clock in all its MIPI CSI2 Receiver IP cores

Raanana, Israel, November 5, 2012: VLSI Plus, a leading provider of MIPI® CSI2 compliant IP cores, today announced the availability of Alias-DT option, which enables outputting multiple pixels per ...
Design-Reuse

VLSI Plus announces an FPGA version of its 64-bit Second Generation MIPI CSI2 Receiver

Raanana, Israel, October 22, 2012: VLSI Plus, a leading provider of MIPI CSI2 compliant IP cores, today announced the availability of the SVRPlus-CSI2-F a 64 bit serial video receiver, supporting ...