EDN

PLL Subsystem architectures for SoC design

Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions. The PLL subsystem is ...
EDN

Choose your PLL lock-time measurement

Rising clock speeds and tighter signal timing has increased demand for accurate high-frequency modules. The PLL (phase-locked loop), which generates a high-frequency output signal based on an input ...
Design-Reuse

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to ...